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LOW SKEW, 1-TO-10, DIFFERENTIAL-TOLVPECL/ECL FANOUT BUFFER
ICS853111A
GENERAL DESCRIPTION
The ICS853111A is a low skew, high perforIC S mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/ HiPerClockSTM E C L Fa n o u t B u f fe r a n d a m e m b e r o f t h e H i Pe r C l o ckS TM fa m i l y o f H i g h Pe r fo r m a n c e Clock Solutions from I DT. The ICS853111A is characterized to operate from either a 2.5V, 3.3V or a 5V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS853111A ideal for those clock distribution applications demanding well defined performance and repeatability.
FEATURES
* Ten differential LVPECL outputs * Two selectable differential LVPECL PCLK/nPCLK clock inputs * PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * Additive phase jitter, RMS: <0.3ps (typical) * Output skew: 23ps (typical) * Part-to-part skew: 85ps (typical) * Propagation delay: 705ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
PCLK0 nPCLK0 PCLK1 nPCLK1 0 1 Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
nQ3 nQ4 nQ5 nQ6 Q3 Q4 Q5 Q6
24 23 22 21 20 19 18 17 VCCO 25 26 27 28 29 30 31 32 1
VCC
16 15 14
VCCO Q7 nQ7 Q8 nQ8 Q9 nQ9 VCCO
Q2 nQ2 CLK_SEL Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9
nQ2 Q2 nQ1 Q1 nQ0 Q0 VCCO
ICS853111A
13 12 11 10 9
VBB
2
CLK_SEL
3
PCLK0
4
nPCLK0
5
VBB
6
PCLK1
7
nPCLK1
8
VEE
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 16, 25, 32 10, 11 12, 13 14, 15 17, 18 19, 20 21, 22 23 , 2 4 26, 27 28, 29 30, 31 Name VCC CLK_SEL PCLK0 nPCLK0 V BB PCLK1 nPCLK1 V EE VCCO nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Output Input Input Power Power Output Output Output Output Output Output Output Output Output Output Pulldown Pullup/Pulldown Pulldown Pulldown Pullup/Pulldown Type Description Positive supply pin. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Negative supply pin. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k
TABLE 3A. CLOCK INPUT FUNCTION TABLE
Inputs PCLKx 0 1 0 1 nPCLKx 1 0 Biased; NOTE 1 Biased; NOTE 1 Outputs Q0:Q9 LOW HIGH LOW HIGH nQ0:Q9 HIGH LOW HIGH LOW Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting
TABLE 3B. CONTROL INPUT FUNCTION TABLE
Inputs CLK_SEL 0 1 Selected Source PCLK0, nPCLK0 PCLK1, nPCLK1
Biased; 0 HIGH LOW Single Ended to Differential Inver ting NOTE 1 Biased; 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1 NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current VBB Sink/Source, IBB Operating Temperature Range, TA Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
6V (LVPECL mode, VEE = 0) -6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5 V 0.5V to VEE - 0.5V 50mA Surge Current 0.5mA -40C to +85C -65C to 150C 37.8C/W (0 lfpm)
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
100mA
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 5.25 85 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 PCLK0, PCLK1 Input Low Current nPCLK0, nPCLK1 Min 2.175 1.405 2.075 1.43 1.86 150 1.2 800 -40C Typ 2.275 1.545 Max 2.38 1.68 2.36 1.765 1.98 1200 3.3 200 -10 -10 Min 2.225 1.425 2.075 1.43 1.86 150 1.2 800 25C Typ 2.295 1.52 Max 2.37 1.615 2.36 1.765 1.98 1200 3.3 20 0 -10 Min 2.295 1.44 2.075 1.43 1.86 150 1.2 800 85C Typ 2.33 1.535 Max 2.365 1.63 2.36 1.765 1.98 1200 3. 3 200 Units V V V V V mV V A A A
-200 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
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TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 Input Low Current PCLK0, PCLK1 -40C Min 1.375 0.605 1.275 0.63 150 1.2 800 Typ 1.475 0.745 Max 1.58 0.88 1.56 0.965 1200 2.5 200 -10 -10 Min 1.425 0.625 1.275 0.63 150 1.2 800 25C Typ 1.495 0.72 Max 1.57 0.815 1.56 0.965 1200 2.5 200 -10 Min 1.495 0.64 1.275 0.63 150 1.2 800 85C Typ 1.53 0.735 Ma x 1.565 0.83 -0.83 0.965 1200 2.5 200 Units V V V V mV V A A A
nPCLK0, nPCLK1 -200 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 PCLK0, PCLK1 Input Low Current nPCLK0, nPCLK1 Min 3.875 3.105 3.775 3.13 3.56 150 1.2 800 -40C Typ 3.975 3.245 Max 4.08 3.38 4.06 3.465 3.68 1200 5 200 -10 -10 Min 3.925 3.125 3.775 3.13 3.56 150 1.2 800 25C Typ 3.995 3.22 Max 4.07 3.315 4.06 3.465 3.68 1200 5 200 -10 Min 3.995 3.14 3.775 3.13 3.56 15 0 1.2 800 85C Typ 4.03 3.235 Max 4.065 3.33 4.06 3.465 3.68 1200 5 200 Units V V V V V mV V A A A
-200 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
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TABLE 4E. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK[0:1], High Current nPCLK[0:1] Input Low Current PCLK[0:1] -40C Min -1.125 -1.895 -1.225 -1.87 -1.44 150 VEE+1.2V 800 Typ -1.025 -1.755 Max -0.92 -1.62 -0.94 -1.535 -1.32 1200 0 200 -10 -10 Min -1.075 -1.875 -1.225 -1.87 -1.44 150 VEE+1.2V 80 0 25C Typ -1.005 -1.78 Max -0.93 -1.685 -0.94 -1.535 -1.32 1200 0 200 -10 Min -1.005 -1.86 -1.225 -1.87 -1.44 150 VEE+1.2V 800 85C Typ -0.97 -1.765 Max -0.935 -1.67 -0.94 -1.535 -1.32 1200 0 200 Units V V V V V mV V A A A
nPCLK[0:1] -200 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375V TO 5.25V; VEE = 0V
Symbol fMAX t PD tsk(o) tsk(pp) t jit tR/tF Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 20% to 80% 85 570 -40C Min Typ >3 670 23 85 0.03 200 315 100 770 35 150 605 Max Min 25C Typ >3 705 23 85 0.03 200 285 85 805 35 150 665 Max Min 85C Typ >3 76 5 23 85 0.03 200 31 5 875 35 150 Max Units GHz ps ps ps ps ps
All parameters are measured 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz
0 -10 -20 -30 -40 -50
band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 155.52MHz
= 0.03ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCO
Qx
SCOPE
VCC nPCLK0, nPCLK1 V
LVPECL
nQx
PP
Cross Points
V
CMR
VEE
PCLK0, PCLK1 VEE
-3.25V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
nPCLK0, nPCLK1 PCLK0, PCLK1 nQ0:nQ9 Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 2A shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input PCLKx
V_REF
nPCLKx
C1 0.1u
R2 1K
FIGURE 2A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin.
VDD(or VCC)
CLK_IN
+ VBB -
C1 0.1uF
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
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LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and V CMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
R1 120 R2 120
nPCLK
HiPerClockS PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 125
nPCLK
HiPerClockS PCL K/n PC LK
R1 1K
R2 1K
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS
PCLK/nPCLK INPUTS For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS
LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination. Figure 6A shows standard termination for 5V LVPECL. The termination requires matched load of 50 resistors pull down to V CC - 2V = 3V at the receiver. Figure 6B shows Thevenin equivalence of Figure 6A. In actual application where the 3V DC power supply is not available, this approached is normally used.
5V
5V 5V PECL Zo = 50 Ohm + Zo = 50 Ohm PECL
R1 125 R2 125 Zo = 50 Ohm PECL 5V R3 84 PECL Zo = 50 Ohm + R4 84
R1 50 3V
R2 50
FIGURE 6A. STANDARD 5V LVPECL OUTPUT TERMINATION
FIGURE 6B. 5V LVPECL OUTPUT TERMINATION EXAMPLE
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SCHEMATIC EXAMPLE
This application note provides general design guide using ICS853111A LVPECL buffer. Figure 7 shows a schematic example of the ICS853111A LVPECL clock buffer. In this example, the input is driven by an LVPECL driver. CLK_SEL is set at logic low to select PCLK0/nPCLK0 input.
Zo = 50 +
Zo = 50
-
VCC
R2 50
R1 50
VCC
C6 (Option) 0.1u
R3 50
Zo = 50 Ohm
Zo = 50 Ohm 3.3V LVPECL R9 50 C8 (Option) 0.1u R10 50 R11 50 R4 1K
1 2 3 4 5 6 7 8
VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO
32 31 30 29 28 27 26 25
VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO
Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6
24 23 22 21 20 19 18 17
U1 ICS853111
VCC Zo = 50 +
VCC=3.3V
Zo = 50 -
(U1-9)
VCC
(U1-16)
(U1-25)
(U1-32)
(U1-1)
R8 50 R7 50
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
C5 0.1uF C7 (Option) 0.1u R13 50
FIGURE 7. EXAMPLE ICS853111A LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111A. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853111A is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.25V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 5.25V * 85mA = 446.3mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 446.3mW + 309.4mW = 755.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.547W * 42.1C/W = 93C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
32-PIN LQFP FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT TM / ICSTM 1-TO-10, LVPECL/ECL FANOUT BUFFER
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.935V (VCC_MAX - VOH_MAX) = 0.935V
*
For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.67V (VCCO_MAX - VOL_MAX) = 1.67V
Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (V
L
CCO_MAX
- VOH_MAX))/R ] * (VCCO _MAX- VOH_MAX) =
L
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (V
L
CCO_MAX
- VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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RELIABILITY INFORMATION
TABLE 8 JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111A is: 1340 Pin compatible with MC100EP111 and MC100LVEP111
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PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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TABLE 10. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS853111AY ICS853111AY 32 Lead LQFP tray -40C to 85C ICS853111AYT ICS853111AY 32 Lead LQFP 1000 tape & reel -40C to 85C ICS853111AYLF ICS853111AYL 32 Lead "Lead-Free" LQFP tray -40C to 85C ICS853111AYFT ICS853111AYL 32 Lead ""Lead-Free"" LQFP 1000 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev A Table Page 11 13 & 14 Description of Change Corrected Figure 5C. Power Considerations - corrected Power(outputs)MAX from 30.2mW to 30.94mW, and revised Junction Temperature and Worse Case Power Dissipation equations. Features section - increased voltage range to 5.25V. Power Supply table - increased maximum VCC to 5.25V. Added 5V LVPECL DC Characteristics table. AC Characteristics table - increased VEE range to -5.25V to 2.375V, and VCC to 2.375V to 5.25V. Corrected Output Load AC Test Circuit Diagram, VEE range from" -1.8V to 0.375V" to "-3.25V to -0.375V". LVPECL clock Input Interface - added another CML driver diagram. Power Considerations - changed Power(core)max from 3.8V to 5.25V and recalculated equations. Absolute Maximum Ratings, corrected Supply Voltage & Negative Supply Voltage from 4.6V & -4.6V to 6V & -6V. Ordering Information Table - added lead-free marking to par t number. Updated datasheets. LVPECL 3.3V DC Characteristics Table - corrected IIH max. from 150A to 200A; and IIL min. from -150A to -200A. LVPECL DC Characteristics Tables - corrected IIH max. from 150A to 200A; and IIL min. from -150A to -200A. ECL DC Characteristics Table - corrected IIH max. from 150A to 200A; and IIL min. from -150A to -200A. Added Termination for 5V LVPECL Output section. Date 10/31/03
T4A T4D T5 B
1 3 4 5 7 11 13 & 14
4/28/04
B B T10 T4B T4C, T4D C T4E
3 17 3 4 5 12
5/14/04 7/6/07
10/25/07
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo, ICS and HiPerClocks are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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